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cool solutions for wireless connectivity xemics sa ? e-mail: info@xemics.com ? web: www.xemics.com datasheet XE1203 lna famp phase shifter lo_buf mmod divider vco pa ch pump pfd ir e f famp rfout tka tkb lfb rfa rfb divctl vco tank loop filter matching network matching network vddf vddd vddp vssf vssd vssp lpf lpf bbamp lim lim oscillator /n clock out demod pattern matching bbamp por ir e f m odulator /n synthesizer fei bitsync xta xtb clkout tsupp tmod(3:0) por clkxtal vdd vdda vss vssa xtal 11 bits barker decoder pattern si dclk data datain XE1203 logic control 11 bits barker encoder rssi control data so sck en sw itch XE1203 433mhz / 868mhz / 915mhz low-power, integrated uhf transceiver general description the XE1203 is a single chip transceiver operating in the 868 and 915mhz license-free ism (industry scientific and medical) frequency bands. its highly integrated architecture allows for minimum external components while maintaining design flexibility. all major rf communication parameters are programmable and most of them can be dynamically set. the XE1203 offers the unique advantage of high data rate communication at rates up to 152.3kbit/s, without the need to modify the number or parameters of the external components. the XE1203 is optimized for low power consumption while offering high rf output power and exceptional rece iver sensitivity. the device is suitable for circuit applications which have to satisfy either the european (etsi-300- 220) or the north american (fcc part 15) regulatory standards. applications ? automated meter reading (amr) ? home automation and access control ? high-quality speech, music and data over rf ? applications requiring konnex-compatibility key product features ? rf output power: up to +15dbm on a 50 ? load (typical) ? high reception sensitivity: down to ?113 dbm (typical) ? low power consumption: r x = 14ma; t x = 62 ma @15dbm (typical) ? supply voltage down to 2.4v ? data rate from 1.2 to 152.3kbps, nrz coding ? konnex-compatible operation mode ? 11-bit barker encoder/decoder ? on-chip frequency synthesizer with steps of 500hz ? continuous phase 2-level fsk modulation ? received data pattern recognition (for wake- up) ? bit-synchronizer for incoming data/clock synchronization and recovery ? rssi (received signal strength indicator) ? fei (frequency error indicator) ordering information part number temperature range package XE1203i063 -40c to +85 vqfn48
2 d0308-214 data sheet XE1203 table of contents 1 functional blo ck diag ram ....................................................................................................... .................. 3 2 pin descr iption................................................................................................................ ............................ 4 3 electrical char acteris tics..................................................................................................... ...................... 5 3.1 absolute maximum operati ng r anges.............................................................................................. ........... 5 3.2 specific ations................................................................................................................. ............................... 5 3.2.1 operati ng r ange ................................................................................................................ ........................... 5 3.2.2 electrical s pecificat ions ...................................................................................................... .......................... 6 4 general d escripti on............................................................................................................ ........................ 8 4.1 detailed de scription ........................................................................................................... ........................... 8 4.1.1 introduc tion................................................................................................................... ................................. 8 4.1.2 receiver ....................................................................................................................... ................................. 8 4.1.3 demodulati on chai n ............................................................................................................. ......................... 9 4.1.4 the demodul ator, ............................................................................................................... ........................... 9 4.1.5 the bit sync hronize r. .......................................................................................................... .........................10 4.1.6 the barker decoder ,............................................................................................................ ........................11 4.1.7 pattern recogni tion bl ock. ..................................................................................................... .......................12 4.1.8 high sensitivity vs. high li nearity: a-m ode, b- mode ............................................................................ ........13 4.1.9 rssi ........................................................................................................................... .................................13 4.1.10frequency error indicator - fei.......................................................................................... .........................14 4.1.11trans mitter .............................................................................................................. ....................................15 4.1.12barke r encodi ng. ......................................................................................................... ................................17 4.1.13clock output for external pr ocessor...................................................................................... ......................18 5 interface definition, pr inciples of operation .................................................................................. ........19 5.1 serial contro l interf ace ....................................................................................................... ........................19 5.2 configuration and st atus regi sters ............................................................................................. ................20 5.2.1 configuration register : general de scripti on .................................................................................... .............21 5.2.2 rtparam configur ation r egister ................................................................................................. .................22 5.2.3 fsparam configur ation r egister ................................................................................................. .................24 5.2.4 switching par ameters........................................................................................................... .......................25 5.2.5 dataout r egister ............................................................................................................... ...........................26 5.2.6 adparam configur ation r egister ................................................................................................. .................27 5.2.7 pattern r egister............................................................................................................... .............................29 5.3 operati ng m odes ................................................................................................................ ........................30 5.3.1 standard power up sequence for the receiver and tr ansmitter...................................................................3 1 5.4 selection of the reference frequenc y........................................................................................... ...............32 5.5 clock output interf ace ......................................................................................................... .......................32 5.6 default settings at powe r-up................................................................................................... ....................32 6 application in format ion ........................................................................................................ ...................33 6.1 matching network of the receiver............................................................................................... .................33 6.2 matching network of the trans mitter ............................................................................................ ...............33 6.3 vco t ank ....................................................................................................................... .............................34 6.4 loop filter of the frequency synt hesiz er....................................................................................... ...............34 6.5 reference crystal for the frequency sy nthesiz er ................................................................................ ........35 6.6 typical app lication ............................................................................................................ ..........................36 7 packaging info rmation .......................................................................................................... ...................37
3 d0308-214 data sheet XE1203 the XE1203 is a single-chip integrated circuit solution intended for use as a low cost fsk transceiver to establish a frequency-agile, half-duplex, bi-directional rf link, with nrz (non-return to zero) data coding. barker encoder/decoder hardware can be activated to modulate/demodul ate the transmitted signal to reduce the effects of fixed-frequency in-band interference. t he device is available in a vqfn48 package and is designed to provide a fully functional multi-channel fsk tr ansceiver. it is intended for applications in the 868mhz european band and the north american 902-928mhz ism band. the single chip tr ansceiver operates down to 2.4 v and provides low power consumption solutions for battery-operated and pow er sensitive applications. the XE1203 is capable of operating data rates as high as 152.3 kbit/s. this makes it ideally suited for applications where high data rates are required. 1 functional block diagram lna famp phase shifter lo_buf mmod divider vco pa ch pump pfd iref famp rfout tka tkb lfb rfa rfb divctl vco tank loop filter matching network matching network vddf vddd vddp vssf vssd vssp lpf lpf bbamp lim lim oscillator /n clock out demod pattern matching bbamp por iref modulator /n synthesizer fei bitsync xta xtb clkout tsupp tmod(3:0) por clkxtal vdd vdda vss vssa xtal 11 bits barker decoder pattern si dclk data datain XE1203 logic control 11 bits barker encoder rssi control data so sck en switch
4 d0308-214 data sheet XE1203 2 pin description pin name i/o description 36 vdd in vdd for low frequency digital blocks 18 vddd in vdd for high frequency digital blocks 29 vdda in vdd for low frequency analog blocks 12 vddf in vdd for high frequency analog blocks 10 vddp in vdd for the power amplifier 42 vss in vss for low frequency digital blocks 19 vssd in vss for high frequency digital blocks 27,25 vssa in vss for low frequency analog blocks 4,16,13 vssf in vss for high frequency analog blocks 7,8 vssp in vss for the power amplifier 5 rfa in rf input 6 rfb in rf input 9 rfout out rf output 14 tka in/out vco tank 15 tkb in/out vco tank 17 lfb in/out loop filter of the pll 26 xta in/out quartz and input of external clock 28 xtb in/out quartz 1,2,3,22,30,31, 47,48 not connected 39 si in data input of the 3-wires interface 35 en in 3-wire interface communication enable signal 38 so out data output of the 3-wires interface 40 sck in input clock of the 3-wires interface 37 switch in/out receiver or transmitter mode selection 43 dclk out transmitter or receiver clock 45 datain in transmitter input data 44 data in/out transmitter input data or receiver output data 41 clkout out output clock at quartz frequency divided by 4, 8, 16 or 32 46 pattern out output of the pattern recognition block 11,20,21,23,24,32, 33, 34 test pins in connected to ground
5 d0308-214 data sheet XE1203 3 electrical characteristics 3.1 absolute maximum operating ranges stresses above those values listed below may cause per manent device failure. exposure to absolute maximum ratings for extended periods may affect device reliability. symbol description min. max. unit vddmr supply voltage -0.5 3.9 v tmr storage temperature -55 125 c the device is esd sensitive and should be handled with precaution. 3.2 specifications 3.2.1 operating range symbol description min. max. unit vddop supply voltage 2.4 3.6 v trop temperature -40 85 c clop load capacitance on digital ports - 25 pf
6 d0308-214 data sheet XE1203 3.2.2 electrical specifications the table below gives the electrical specificati ons of the transceiver under the following conditions: supply voltage = 3.3 v, temperature = 25 c, 2-le vel fsk without pre-filtering, fc = 915 mhz, ? f = 55 khz, bit rate = 4.8 kb/s, bw dsb = 200 khz, ber = 0.1 % (at the output of the bit synchronizer), matched impedances, environment as defined in section 6, unless otherwise specified. symbol description conditions min typ max unit iddsl supply current in sleep mode - 0.2 1 a iddst supply current in standby mode quartz oscillator (39 mhz) running - 0.85 1.10 ma iddr supply current in receiver mode - 14 17 ma iddt supply current in transmitter mode rfop = 5 dbm rfop = 15 dbm - - 33 62 40 75 ma ma br = 4.8 kbit/s mode a - -113 -110 dbm br = 4.8 kbit/s mode b - -100 -97 dbm br = 32.7 kbit/s mode a - -107 -104 dbm br = 32.7 kbit/s mode b - -94 -91 dbm br = 152.3 kbit/s mode a (*) - -100 -97 dbm rfs rf sensitivity (?) ? f = 200 khz, bw dsb = 600 khz br = 152.3 kbit/s mode b (*) - -87 -84 dbm br = 1154 bit/s mode a - -113 -110 dbm rfsb rf sensitivity with barker coding/decoding br = 1154 bit/s mode b - -100 -97 dbm fda frequency deviation programmable 1 - 255 khz ccr co-channel rejection -13 -10 - dbc iip3 input intercept point funw = f lo + 1 mhz and f lo + 1.945 mhz mode a mode b -43 -28 -40 -25 - - dbm dbm ml receiver input level - - -5 dbm bw base band filter bandwidth dsb programmable - - 200 600 - - khz khz acr adjacent channel rejection funw = f lo + 650 khz pw= - 108 dbm (mode a) 45 48 - dbc br bit rate programmable 1.2 152.3 kb/s rfop rf output power programmable. on a 50 ? load. rfop10 rfop1 rfop20 rfop2 -3 +2 +7 +12 0 +5 +10 +15 - - - - dbm dbm dbm dbm fr synthesizer frequenc y range programmable each range with its own external components 433 868 902 - - - 435 870 928 mhz mhz mhz ts_tr transmitter wake-up time from oscillator running - 200 250 s ts_re receiver baseband wake-up time from oscillator running - 1.5 1.8 ms
7 d0308-214 data sheet XE1203 symbol description conditions min typ max unit ts_rssi rssi wake-up time from receiver running - - 1 ms ts_os quartz oscillator wake-up time fundamental 3 rd overtone - - 1 7 2 - ms ms ts_fei fei wake-up time - - 2/br ms ts_sync_a q time for synchronization of the barker decoder input power of ?106 dbm data rate = 1154 bps chip rate = 12.7 kcps from rx running - 5 - ms xtal quartz oscillator frequency fundamental or 3 rd overtone - 39 - mhz fstep frequency synthesizer step exact step is xtal / 77?824 - 500 - hz vthr equivalent input thresholds of the rssi mode a low range:vthr1 vthr2 vthr3 high range:vthr1 vthr2 vthr3 - - - - - - -100 -95 -90 -85 -80 -75 - - - - - - dbm dbm dbm dbm dbm dbm spr spurious emission in receiver mode - -55 -50 dbm vih digital input level high in % vdd 75 - - % vil digital input level low in % vdd - - 25 % voh digital output level high in % vdd 75 - - % vol digital output level low in % vdd - - 25 %
8 d0308-214 data sheet XE1203 4 general description the XE1203 is a direct conversion (zero-if) half-duplex dat a transceiver. it includes a receiver, a transmitter, a frequency synthesizer and some service blocks. the circ uit operates in three frequency ranges (433 mhz, 868mhz and 915mhz) and uses 2-level fsk modulation. in a ty pical application, the XE1203 is programmed by a microcontroller through the 3-wire serial bus si, so, sck to write to and read from the configuration registers. the XE1203 consists of 4 main functional blocks. the receiver converts the incoming 2-level fsk modulated signal into a synchronized bit stream. the receiver is composed of a low-noise amplifier, down-conversion mi xers, base band filters, base band amplifiers, limiters, demodulator and bit synchronizer. the bit synchronizer trans forms the data output of the demodulator into a glitch- free bit stream data and generates a synchronized clo ck dclk to be used to sample the data signal easily without loading an external processor with heavy signal proc essing. in addition, the receiver includes a received signal strength indicator function (rssi ), a frequency error indicator function (fei) that gives indication about the frequency error of the local oscillator, and pattern recogni tion function to detect programmable reference word in the incoming bit stream. a user-selectable barker codi ng/decoding block can be activated to spread the data with an 11-bit barker code upon transmission and decode the data upon reception by making a correlation between the spread data and the same 11-bit barker code. the bandwid th of the base-band filters, the frequency deviation of the expected incoming fsk signal as well as the bi t rate of this bit stream are programmable. the transmitter performs the modulation of the carrier by an input bit stream and the transmission of the modulated signal. the modulation is made directly through the frequency synthesizer. an on-chip power amplifier then amplifies the signal. the output power is progra mmable among 4 possible values. the frequency deviation and the bit rate for the transmit signal are the same as those programmed for the receiver section. the frequency synthesizer generates the local oscillator (lo) signal fo r the receiver section as well as the fsk modulated signal for the transmitter secti on. the core of the synthesizer is implemented with a delta-sigma pll architecture. the frequency is programmable with a step of 500 hz in 3 frequency bands, 433-, 868-, and 915- mhz. this section includes a crystal oscillator whose signal is the reference for the pll. this reference frequency can also be used as a reference clock for the external microcontroller through clkout pin with a user selectable division ratio of 4,8,16 or 32. the control block generates the control signals according to the se tting in its set of configuration registers. the service block performs all the necessary functions for the circuit to work properly, including the internal voltage and current sources. 4.1 detailed description 4.1.1 introduction the pin data is used in both transmitter and receive secti ons and by default it is set to bidirectional mode. in receiver mode, data holds the recove red information. in transmitter mode, the information to be sent applied to this pin. if a unidirectional mode is required, the user ha s to set adparam_disable_data_bidir to ?1?. in this case, pin data in an output mode used by receiver se ction and pin datain is used for transmit data. 4.1.2 receiver the receiver section has two output signals indicating recovered clock (pin dclk) and recovered nrz data (pin data). the bit synchronizer controls the recovered clock dclk pin. if t he bit synchronizer is enabled by setting the bit ?rtparam_bitsync? to ?1? the dclk pin outputs the clock recove red from the incoming data stream. disabling bit synchronizer holds the dclk pin at low level and connects the demodulator output to data pin. the function of bit synchronizer is to remove the glitches from the bit stream data and to provide the synchronous output clock at dclk. the output data is valid at the rising edge of the dclk.
9 d0308-214 data sheet XE1203 4.1.3 demodulation chain the demodulation part is composed of an fsk demodulator , a bit synchronizer, a barker decoder and a pattern recognition block. the next figure show s the interaction between each block. fsk demodulator barker decoder bit synchronizer pattern recognizer data control data dclk pattern pow pow pow rtparam_bitsync rtparam_barker rtparam_pattern data dclk data dclk fsparam_br adparam_psize adparam_ptol adparam_pattern data figure 1 demodulation architecture. 4.1.4 demodulator the demodulator provides a bit stream from the received fsk modulated base band limited signals, i_lim and q_lim. if rtparam_bsync and rtparam_barker bits are se t low, i.e disabled, then the demodulator output is directly connected to the data pin and the dclk pin is set to low. the modulation index required for prop er operation of the demodulator is: , 2 2 = ? ? br f where ? f corresponds to the frequency deviation and br corresponds to the bit rate.
10 d0308-214 data sheet XE1203 4.1.5 bit synchronizer the output of the demodulator has glitches and jitters. the bit synchronizer transfo rms the data output of the demodulator into a glitch-free bit stream data and gener ates a synchronized clock dclk to be used for sampling the data output (see below). data (nrz) dclk figure 2. bit synchronizer timing diagram. to ensure proper behaviour of the bit synchronizer, three c onditions have to be satisfied: a preamble of 24 bits is required for the synchronization; this preamble must be a sequence of ?0? and ?1? sent alternatively, during transmission of data, the bit stream must have at least one transition from ?0? to ?1? or from ?1? to ?0? every 8 bits. the accuracy of the bit rate must be better than 5 %. the bit synchronizer is on when rtparam_bsync is high. fsparam_br defines the bit rate in the following way. bit rate = 1 0)) : m_br(6 int(fspara 3 34 . 152 + e , where int(x) is the integer value of the unsigned binary representat ion of x. if the konnex standard is used then the bit rate is fi xed and equal to 32.77 kbps. the register fsparam_osr (address ?00101? ) has to be set to ?00011110? , the regi ster fsparam_br(6:0) has to be set to ?000x0000? and the bit fsparam_change_osr has to be set to ?1?.^
11 d0308-214 data sheet XE1203 4.1.6 barker decoder the barker decoder is an alternative to the bit synchronizer for a fixed data rate of 1154 bps . the barker block is selected in receiver mode when rtparam_barker is high. in transmission, the information data at a bit rate of 1154 bps is spread using an 11 bits barker code. the result is a bit stream at 12.7 kilo chips per second (kcps), which is applied to the frequency synthesizer. at the receiver par t, the signal is demodulated using the fsk demodulator (at 12.7 kcps) and fed to the barker decoder that provides a information data stream (1154 bps) and a synchronized clock to sample it. the following figure describes the coding/decoding process. barker encoder 11 bit barker code fsk modulator information data 1154 bps encoded information 12.7 kcps chip rate = 12.7 kcps fsk demodulator barker decoder 11 bit barker code demodulated chips with some residual jitter. chip rate = 12.7 kcps data dclk data out (information recovered) dclk = 1.145 khz data rate = 1.145 kbps figure 3. data encoding decoding channel. in reception mode, the chip provides a clock (dclk) to a microcontroller. the data can be sampled at the rising edge of the clock. when using the barker coding decoding proc ess, dclk is used to detect the sync acquisition. if there is no valid data, dclk remains high. the first falli ng edge of the clock means that the sync acquisition phase is reached and the data has became available. the nex t figure shows the data exchange during the reception mode.
12 d0308-214 data sheet XE1203 information data from a microcontroller bit rate = 1154 bps dclk @1154 hz bit1 bit2 bit3 bit4 bit5 bit6 spread data @12.7 kchps bit0 spread bit0 spread bit1 spread bit2 spread bit3 spread bit4 spread bit5 figure 4 data exchange during recepti on mode when barker scheme is used. 4.1.7 pattern recognition block this feature can be activated by setting rtparam_pattern to high while in receiver mode. the incoming nrz bit stream is compared with a pattern stored in patparam_ pattern registers. the patte rn output is driven by the output of this comparator and is sync hronized by dclk. it is set to high when a matching condition is detected, otherwise set to low. pattern output is updated at the rising edge of dcl k. the number of bits used for comparison is defined in adparam_psize register and the num ber of tolerated errors for the pattern recognition is defined in adparam_ptol register. the next figure shows the pattern matching operation. data (nrz) dclk bit n-x = pattern[x] bit n-1 = pattern[1] bit n = pattern[0] pattern figure 5. pattern matching operation.
13 d0308-214 data sheet XE1203 4.1.8 high sensitivity vs. high linearity: a-mode, b-mode the receiver can be operated in two different modes that pr ovide the highest sensitivity or the highest linearity. two operating mode is selectable via the registers ? swparam_rmode1 ? or ? swparam_rmode2 ? (see the configuration register section). in a-mode, the re ceiver has the highest sensitivity (s ee rfs parameter) and in b-mode, the receiver has the highest linearity (see iip3 parameter) 4.1.9 rssi this function provides a received si gnal strength indication based on the signal level at the output of the base- band filter. to activate this function, the bit ?rtparam_rssi? (see the configurat ion register section) must be set to ?1?. when activated, the 2-bits stat us information is stored in register ?dataout_rssi? and can be read through the serial control interface. the meani ng of this status information is given in the table below, where v rffil is the differential amplitude of the equivalent input rf signal w hen the receiver is operated in a-mode. the thresholds vthri are the thresholds at the output of the base-band filter divided by the gain between the input of the receiver and this output. dataout_rssi description 0 0 v rffil vthr1 0 1 vthr1 < v rffil vthr2 1 0 vthr2 < v rffil vthr3 1 1 vthr3 < v rffil table 1 rssi status description the operating range of rssi measurement can be changed by programming rtparam_rssir register, this way two ranges with three vthri values can be selected. the time diagram of an rssi measurement is given in the next figure. when the rssi function has been activated the signal strength is periodica lly measured and the result is stored in the register ?dataout_rssi ? each time ?dataout_rssi? is read via the 3 wires interface. ts_rs is the wake-up time required after the function has been activated to get a valid result. xxx val1 val2 val3 val4 0 val5 val1 val4 xxx ts_rssi saout_rssi rssi_out en rtparam_rssi dataout_rssi figure 6. rssi measurement timing diagram
14 d0308-214 data sheet XE1203 saout_rssi is internally generated signal during a r ead sequence of dataout_rssi register and used for updating dataout_rssi register. the next figure shows the timing diagram of the saout_rssi generation. a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 sck si en so hz hz saout_rssi figure 7. generati on of saout_rssi the maximum frequency of sck during the read operation of the rssi value is 100 khz. 4.1.10 frequency error indicator - fei this function provides information about the frequency error of the local oscillator compared with the input carrier frequency and can be used to implement afc. the condition on the modulation index fo r proper behaviour of the fei function is: , 2 2 = ? ? br f where ? f is the frequency deviation and br is the bit rate. important note the time diagram of an fei measurement is given in the next figure. when the fei block has been woken up and is ready, and as long as the block is kept on, the fr equency error is measured and the current result of the measurement is loaded in the register ?dataout _msb_fei? and ?dataout_lsb_fei ?? each time the ?dataout_lsb_fei ?? register is read. ts_fei is the time required for the first evaluation to be completed after the block has been started up and its value is gi ven in section 3.2. since the content s of the configuration register is validated at the rising edge of the enable signal ?en?, the fei block is actually started up at this time.
15 d0308-214 data sheet XE1203 xxx first evaluation val0 val1 val2 val3 0 val4 val1 val3 xxx ts_fei saout_fei fei_out en rtparam_fei dataout_msb_fei& dataout_lsb_fei 2/br figure 8 time diagram of an fei measurement. to guarantee proper behaviour of the fei, the sum of t he frequency offset and the signal bandwidth (single sided) should be lower than the baseband filter bandwidth (single sided). that is: f offset + signalbw < baseband_filterbw. where f offset is the difference between the carrier frequenc y and the lo frequency, signalbw is the signal bandwidth (single side) equal to the sum of the bit rate divided by 2 and the frequency deviation ( br/2 + df), and baseband_filterbw is the channel filter bandwid th defined by rtparam_bw parameters. the frequency error can be calculated by the following formula: the frequency error = (br/8) *int(dataout_fei(11:0)), where dataout_fei(11:0) = dataout_m sb_fei(3:0) & dataout_lsb_fei(7:0) and int(x) is the integer value of the signed binary representation of x. saout_fei is internally generated during a read sequence of ?dataout_lsb_fei ?? register in the same way as saout_rssi. the maximum frequency of sck during the read operation of the rssi value is 100 khz. when using the konnex standard, the bit adparam_enabl e_konnex (address ?01111?) has to be set to ?1?. 4.1.11 transmitter the transmit data should be applied to data or da tain pins depending on the adparam_disable_data_bidir register setting. if it is set to high (?1?) the datain pin is used otherwise bidirectional pin data is used for transmit data. the modulation of lo with the data applied can be per formed with pre-filtering or without. the pre-filtering can be selected by setting rtparam_filter register to hi gh (?1?). so, the modulation of the lo frequency by the bit stream can be made in two ways: ? the input bit stream is directly applied to t he frequency synthesizer wit hout any pre-filtering, ? the input bit stream is pre-filtered before being appli ed to the frequency synthesizer ; with this filtering, each edge of the bit stream is linearly smoothed with a staircase transition. the two possible ways of modulation are shown in fi gure 4-9, where ?datain? is the input bit stream.
16 d0308-214 data sheet XE1203 t rise t bit datain or data no filtering stairecase filtering in freq_synth in freq_synth figure 9. modulation with and without pre-filtering the characteristic of the filtering is the ratio t rise /t bit . the value of this ratio is programmable on two values with the register ?rtparam_stair?, as shown in the following table. rtparam_stair t rise /t bit 0 10 % 1 20 % when using the filtering option i.e. ?r tparam_filter? set ?1?, only the following bit rates and frequency deviations can be used. fsparam_dev frequency deviation 00101000 00110111 01010000 10100000 11001000 40 khz 55 khz 80 khz 160 khz 200 khz
17 d0308-214 data sheet XE1203 fsparam_br bit rate (bps) 1111110 0111111 0011111 0001111 0000111 0000011 0000001 others 1200 2400 4800 9600 19200 38400 76800 153000 if adparam_enable_konex is high, then the filtering option is available for a bit rate of 32.7 kbps and one of the frequency deviations defined above. 4.1.12 barker encoding. when using the barker encoding in transmitter mode, the rt param_barker parameter has to be set to ?1? and the information data stream at 1154 bps is applied thr ough the pin data or datain according to the adparam_disable_data_bidir parameter. this data is spread into a chip stream at 12.7 kchps into the barker encoder. this chip stream is directly applied to the frequency synthesizer without any pre-filtering. the dclk pin is used for data clock in the transmission mode and this clock is generated by XE1203. the dclk is applied to the microcontroller, at the falling edge of the each clock a new data bit is supplied by microcontroller. the data is sampled by XE1203 at the rising edge of dclk and spread by using an 11-bit length barker code. the following figure shows the data exchange during t he transmission mode when barker option is used. information data from a microcontroller bit rate = 1154 bps dclk @1154 hz bit1 bit2 bit3 bit4 bit5 bit6 spread data @12.7 kchps bit0 spread bit0 spread bit1 spread bit2 spread bit3 spread bit4 spread bit5 figure 10 data exchange during transmission mode.
18 d0308-214 data sheet XE1203 4.1.13 clock output for external processor a reference clock could be generated by XE1203 to the external microcontroller. rtparam_cl kout register controls the clkout pin. when it is set to high then clkout is activated. the generated clo ck can be 1/4, 1/8, 1/16 or 1/32 of the XE1203 reference oscillator. the differ ent divider ratios can be selected by programming ?adparam_clkfreq? register (see the c onfiguration register section below). the reference oscillator frequency of 39mhz can result 1.22, 2.44, 4.87 or 9.75mhz clock at the clkout pin. this clock is stopped in sleep mode.
19 d0308-214 data sheet XE1203 5 interface definition, principles of operation 5.1 serial control interface a 3-wire bi-directional bus (sck, si, so) is used to communicate with XE1203. sck and si are input signals supplied externally, for example by the microcontroller. the XE1203 configur es the so signal as an output pin during read operation, and it is tri-stated in other modes. the falling edge of the sck signal is used to sample the si pin to write data into the internal shift register of the XE1203. the rising edge of t he sck signal is used to output data to so pin by XE1203, so the microcontroller should sample data at the falling edge of sck. the signal en must be low during the whole write and read sequences. in write mode t he actual content of the configuration register is updated at the rising edge of the en signal. before this, the new data is stored in temporary registers whose content does not affect the transceiver settings. the timing diagram of a write sequence is given in t he figure below. the sequence is initiated when a start condition is detected, that is when the si signal is set to ?0? during a period of sck. the next bit is a read/write (r/w) bit which should be ?0? to indicate a write operation. the next 5 bits are the addre ss of the control register a[4:0] to be accessed, msb first. then, the next 8 bits are the data to be wr itten in the register. the sequence ends with 2 stop bits set to ?1?. the data on si should change at the rising edges of sck, and is sampled at the falling edge of sck. after the 2 stop bits, the data transfer is term inated. the si line should be at ?1? for at least one clock cycle on sck before a new write or read sequence can start. in doing this, users can do multiple registers write without rising en signal in betw een. the duty cycle of sck must be between 40 % and 60 % and the maximum frequency of this signal is 1 mhz except when readi ng the rssi output and fei output where the maximum frequency of sck is limited to 100 khz. over the operati ng supply and temperature range, set-up and hold time for si on the falling edge of sck are 200ns. the register at address 0 is one bit length and used to defi ne the configuration of the chip. when writing in this register, the sequence described above is valid except t hat only one bit data is needed instead of 8 bits. if a unique write procedure is used for all registers then, when writi ng at address 0, 8 data bit are sent but only the msb is valid and written at address 0. the remaining 7 data bits must be all ones. a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 sck si en so hz figure 11 write sequence into configuration register the following figure shows a write sequence at address zero. a4 a3 a2 a1 a0 d7 sck si en so hz figure 12 write sequence into configur ation register at address zero.
20 d0308-214 data sheet XE1203 the time diagram of a read sequence is given in figure below. the sequence is initiat ed when a start condition is detected, that is when the si signal is set to ?0? during a period of sck. the next bit is a read/write (r/w) bit which should be ?1? to indicate a read operation. the next 5 bits are the address of the cont rol register a[4:0] to be accessed, msb first. then the data from the register are transmitted on the so pin. the data become valid at the rising edges of sck and should be sampled at the falling edge of sck. after this, the data transfer is terminated. the si line must stay high for at l east one clock cycle on sck to start a new write or read sequence. the maximum current drive on so is 2ma @ 2.7v, the maximum load is clop. when the serial interface is not used for read or write oper ations, both sck and si should be set to ?1?. except in read mode, so is set to ?hz?. a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 sck si en so hz hz figure 13 read sequence of c onfiguration register. when reading the register at address zero, the timing diagram is the following one. a4 a3 a2 a1 a0 d7 sck si en so hz hz figure 14 read sequence of configur ation register at address 0. 5.2 configuration and status registers the transceiver has several operating modes and parameter s, which can be selected by the user. some of these modes and all the parameters are stored in an internal configuration register t hat can be accessed by the microcontroller through a 3-wires serial interface. the switching option allows some parameters to be changed rapidly; defined in swparam registers, by using the 3-wire interface in a reduced sequence or by using a single input pin switch. the configuration is defined by the ch ip_config parameter (address 0) when rt param_switch_ext is low or by the pad switch when rtparam_switch_ext is high. using chip_c onfig or switch allows switching between a set of two predefined parameters of the transceiver. if a parameter must not change then it must be set at the same value in the two registers used to define it. to switch between configurations, the new value of chip_config or switch should be modified when the en signal is low. the act ual change will be applied to the transceiver upon the rising edge of the en signal. the following table summa rizes the chip configuration programming.
21 d0308-214 data sheet XE1203 chip_config address 0 switch (pad) rtparam_switch_ext registers used 0 pad switch is an output : ?1? in transmitter mode ?0? in the other mode 0 swparam_mode_1 swparam_power_1 swparam_rmode_1 swparam_t_delsig_in_1 swparam_freq_1 1 pad switch is an output : ?1? in transmitter mode ?0? in the other mode 0 swparam_mode_2 swparam_power_2 swparam_rmode_2 swparam_t_delsig_in_2 swparam_freq_2 x 0 1 swparam_mode_1 swparam_power_1 swparam_rmode_1 swparam_t_delsig_in_1 swparam_freq_1 x 1 1 swparam_mode_2 swparam_power_2 swparam_rmode_2 swparam_t_delsig_in_2 swparam_freq_2 by default configuration 1 is used and rtparam_switch_ext is set to ?0?. 5.2.1 configuration register: general description name size address description config 1 x 1 0 switch configuration rtparam 2 x 8 00001 - 00010 parameters of the receiver and transmitter fsparam 3 x 8 00011 - 00101 frequency parameters swparam 6 x 8 00110 - 01011 switching parameters dataout 2 x 8 01100 - 01101 data provided by internal blocks of the transceiver adparam 5 x 8 01110 - 10010 additional parameters pattern 4 x 8 10011 - 10110 reference pattern for the ?pattern recognition? function in addition, 9 bytes at addresses 10011 to 11 100 are reserved for test purposes. name size address description test 9 x 8 10 011 ? 11 100 test of the circuit (reserved) all the bits that are referred as ?reserved? in the table above and in the following ones should be set to ?0?.
22 d0308-214 data sheet XE1203 5.2.2 rtparam configuration register the detailed description of the ?rtparam? register is given in the next table. name bits address description chip_config 0 00000 chip configuration: 0 -> config 1 1 -> config 2 rtparam_bitsync 7 00001 bit synchronizer on/off: 0 -> off 1 -> on rtparam_barker 6 00001 barker on/off: 0 -> off 1 -> on rtparam_rssi 5 00001 rssi_on/off: 0 -> off 1 -> on rtparam_rssir 4 00001 range of the rssi: 0 -> low range 1 -> high range rtparam_fei 3 00001 fei on/off 0 -> off 1-> on rtparam_bw 2 00001 bandwidth of the bb filter 0 -> 200 khz (dsb) 1 -> 600 khz (dsb) rtparam_osc 1 00001 source of reference frequency 0 -> internal quartz oscillator 1 -> external signal rtparam_clout 0 00010 enable of clkout: 0 -> no signal provided on pad clkout 1 -> signal at quartz frequency divided by 4,8,16,or 32 provided on pad clkout (9.75mhz down to 1.22 mhz) rtparam_stair 7 00010 rising and falling times in case of pre-filtering in transmitter mode: 0 -> 10 % of bit duration 1 -> 20 % of bit duration
23 d0308-214 data sheet XE1203 name bits address description rtparam_filter 6 00010 pre-filtering of the bit stream in transmitter mode 0 -> no filtering 1 -> filtering the filtering function is available only for the following bit rates and frequency deviations: fspanam_br = "1111110" -> br = 1200 bps fspanam_br = "0111111" -> br = 2400 bps fspanam_br = "0011111" -> br = 4800 bps fspanam_br = "0001111" -> br = 9600 bps fspanam_br = "0000111" -> br = 19200 bps fspanam_br = "0000011" -> br = 38400 bps fspanam_br = "0000001" -> br = 76800 bps fsparam_dev = "00101000" -> ? f = 40 khz fsparam_dev = "00110111" -> ? f = 55 khz fsparam_dev = "01010000" -> ? f = 80 khz fsparam_dev = "10100000" -> ? f = 160 khz fsparam_dev = "11001000" -> ? f = 200 khz rtparam_modul 5 00010 inhibition of the modulation in transmitter mode: 0 -> modulation 1 -> no modulation rtparam_iqamp 4 00010 iq amplifiers on/off: 0 -> off 1 -> on rtparam_switch_ext 3 00010 mode of switch: 0 -> configuration defined by chip_config and pad switch is an output that indicates t he rx or tx mode of the chip 1 -> configuration defined by the pad switch used as an input rtparam_pattern 2 00010 pattern recognition on/off: 0 -> off 1 -> on
24 d0308-214 data sheet XE1203 5.2.3 fsparam configuration register the detailed description of the ?fsparam? register is given in the next table. name bits address description fsparam_band 1-0 00010 frequency band: 00 -> 216 ? 218 mhz 01 -> 433 ? 435 mhz 10 -> 868 ? 870 mhz 11 -> 902 ? 928 mhz fsparam_dev 7-0 00011 frequency deviation: ? f =int( fsparan_dev) * 1 khz, where int(x) = integer value of the binary represent ation of x. example: 00000001 -> ? f = 1 khz 11111111 -> ? f = 255 khz fsparam_change_osr 7 00100 change osr 0 -> default bit rate defined by fsparam_br 1 -> used with konnex standard fsparam_br 6-0 00100 bit rate: br = 152.34e3/(int(fsparam_br)+1), where int(x) = integer value of the binary represent ation of x. example: 0000000 -> br = 152.34 kbps 1111111 -> br = 1.19 kbps 0000100 -> br = 32.7 kbps used in konnex mode fsparam_osr 7-0 00101 ?00011101? with konnex standard and fsparam_change_osr = ?1? else ?00000000?
25 d0308-214 data sheet XE1203 5.2.4 switching parameters the detailed description of the ?swparam? register is given in the next table. name bits address description swparam_mode_1 7-6 00110 chip mode configuration 1: 00 -> sleep mode 01 -> stand by mode 10 -> receiver mode 11 -> transmitter mode swparam_power_1 5-4 00110 transmitter output power configuration 1: 00 -> 0 dbm 01 -> 5 dbm 10 -> 10 dbm 11 -> 15 dbm swparam_rmode_1 3 00110 receiver mode configuration 1: 0 -> mode a (high sensitivity) 1 -> mode b (high linearity) swparam_t_delsig_in_1 2-0 00110 extension of the i nput vector of the sigma-delta modulator configuration 1 swparam_freq_1 7-0 7-0 00111 01000 lo frequency in 2?s complement representation configuration 1: 00?0 -> flo = middle of the range 0x?x-> flo = higher than the middle of the range 1x?x-> flo = lower than the middle of the range swparam_node_2 7-6 01001 chip mode configuration 2: 00 -> sleep mode, 01 -> stand by mode, 10 -> rx mode, 11 -> tx mode, swparam_power_2 5-4 01001 transmitter output power configuration 2: 00 -> 0 dbm 01 -> 5 dbm 10 -> 10 dbm 11 -> 15 dbm swparam_rmode_2 3 010001 receiver mode configuration 2: 0 -> mode a (high sensitivity) 1 -> mode b (high linearity) swparam_t_delsig_in_2 2-0 01001 extension of the i nput vector of the sigma-delta modulator configuration 2 swparam_freq_2 7-0 7-0 01010 01011 lo frequency in 2?s complement representation configuration 2: 00?0 -> flo = middle of the range 0x?x-> flo = higher than the middle of the range 1x?x-> flo = lower than the middle of the range
26 d0308-214 data sheet XE1203 here are examples of lo frequency settings in fsparam_freq when mode 2 is used. byte address 01010 bit 7 bit 0 byte address 01011 bit 7 bit 0 resulting lo setting note: reference frequency = 39.0 mhz 00000000 00000000 f0, where f0 depends on the selected frequency band (see fsparam_band ) f0 = 434.0 mhz for the 433-435 mhz band f0 = 869.0 mhz for the 868-870 mhz band f0 = 915.0 mhz for the 902-928 mhz band 00000000 00000001 f0 + 500 hz 00000000 00000010 f0 + 2 * 500 hz 11111111 11111111 f0 ? 500 hz 11111111 11111110 f0 ? 2 * 500 hz 5.2.5 dataout register the detailed description of the ?dataout? register is given in the next table. name bits address description dataout_rssi 7-6 01100 rssi output: 0 0 -> lowest level 0 1 -> 2 nd level 1 0 -> 3 rd level 1 1 -> highest level reserved 5-4 01100 set to zero dataout_msb_fei 3-0 01100 fei output (msb) dataout_lsb_fei 7-0 01101 fei output (lsb) ferror = (br/8)*int(dataout_msb_fei & dataout_lsb_fei) where int(x) = integer value of the binary representation of x.
27 d0308-214 data sheet XE1203 5.2.6 adparam configuration register the detailed description of the ?adparam? register is given in the next table. name bits addres s description adparam_psize 7-6 01110 size of the reference pattern: 0 0 -> 8 bits 0 1 -> 16 bits 1 0 -> 24 bits 1 1 -> 32 bits adparam_ptol 5-4 01110 number of tolerated errors for the pattern recognition: 00 -> 0 error 01 -> 1 error 10 -> 2 errors 11 -> 3 errors adparam_clk_freq 3-2 01110 frequency of clkout 00 -> 1.22 mhz (div ratio :32) 01 -> 2.44 mhz (div ratio :16) 10 -> 4.87 mhz (div ratio :8) 11 -> 9.75 mhz (div ratio :4) adparam_invert 1 01110 inversion of the output data of the receiver: 0 -> default data 1 -> inverted data adparam_regbw 0 01110 regulation of the bandwidth of the base-band filter on/off: 0 -> on 1 -> off adparam_regfreq 7 01111 periodicity of r egulation of the bandwidth of the base-band filter: 0 -> only at start-up of the receiver 1 -> each minute (by default) or every 7 sec (test mode) as long as the receiver is on. adparam_regcond 6 01111 regulation process of the bandw idth of the base-band filter according to the selected bandwidth: 0 -> regulation restarted each time the bandwidth is changed 1 -> no regulation started when the bandwidth is changed adparam_xsel 5 01111 selection of the xosc modes: 0 -> cl+c0 = 7 pf 1 -> cl+ c0 = 11 pf, lower consumption
28 d0308-214 data sheet XE1203 name bits address description adparam_resxosc 4-1 01111 selection of the value of the resistor put between tka and tkb in order to use a crystal operating on its third overtone 0000 -> resistance = 3800 k ? 0001 -> resistance = 2.55 k ? 0010 -> resistance = 4.65 k ? 0011 -> resistance = 1.78 k ? 0100 -> resistance = 8.79 k ? 0101 -> resistance = 2.07 k ? 0110 -> resistance = 3.22 k ? 0111 -> resistance = 1.56 k ? 1000 -> resistance = 16.55 k ? 1001 -> resistance = 2.26 k ? 1010 -> resistance = 3.79 k ? 1011 -> resistance = 1.66 k ? 1100 -> resistance = 6.04 k ? 1101 -> resistance = 1.91 k ? 1110 -> resistance = 2.81 k ? 1111 -> resistance = 1.48 k ? adparam_enable_konnex 0 01111 use of the konnex standar d when using the fei 0 -> normal mode 1 -> konnex standard => br = 32.7 kbps this modifies osr adparam_chge_thres 7 10000 make the sync and acquisition threshold programmable, and allow the change of the barker code: 0 -> threshold are hard-coded and sync loss counter is 50 bits 1 -> threshold are defined by bparam_sync_thres and bparam_trac_thres sync loss counter is variable and defined by adparam_sync_loss adparam_sync_thres 6:0 10000 threshold for sync acquisition in baker mode adparam_disable_data_bidi r 7 10001 disable data bidir 0 -> pad data used in bidirectional mode. 1 ->pad data used as output and pad datain used as input. adparam_trac_thres 6-0 10001 threshold for tracking baker mode reserved 7 10010 adparam_sync_loss 6-0 10010 number of bits before sync loss for barker decoding algorithm.
29 d0308-214 data sheet XE1203 5.2.7 pattern register this register holds the user supplied reference pattern of 8, 16, 24, or 32 bits (see adparam_psize parameter). the first byte of this pattern is always stored in t he byte at address a[4:0] = 10011. depending on the pattern size the pattern values stored in addresses 10011, 10100, 10101 and 10110. the addresses 10011, 10100, 10101 and 10110 hold the first, second, third and fourth bytes of the re ference pattern value respectively. the msb bit of the reference pattern is always the bit 7 of the address 10011. when compared to the demodulated bit stream, the last bit received is compared to the lsb bit in the pattern register. the ?oldest? bit received (the first of the last 8, 16, 24, or 32 received bits, depending on adparam_psize) is compared with the bit 7 of byte address 10011 (the msb). name bits byte address description patparam_pattern 7-0 10011 10100 10101 10110 1 st byte of the reference pattern 2 nd byte 3 rd byte 4 th byte example of pattern recognition with a 32-bit pattern: byte address 10011 bit 7 bit 0 byte address 10100 bit 7 bit 0 byte address 10101 bit 7 bit 0 byte address 10110 bit 7 bit 0 10010011 10101010 10010011 10101010 101 10010011 10101010 10010011 10101010 previous bits from demodulator last bit received example of pattern recognition with an 8-bit pattern: byte address 10011 bit 7 bit 0 byte address 10100 bit 7 bit 0 byte address 10101 bit 7 bit 0 byte address 10110 bit 7 bit 0 10010011 xxxxxxxx x xxxxxxx xxxxxxxx 101 10010011 previous bits from demodulator last bit received
30 d0308-214 data sheet XE1203 5.3 operating modes the XE1203 has 4 main operating modes illustrated in table below. these modes are defined in register swparam_mode_1 when the configuration 1 is chosen or swparam_mode_2 when the configuration 2 is chosen. the configuration is defined by the ch ip_config parameter (address 0) when rt param_switch_ext is low or by the pad switch when rtparam_switch_ext is high. using ch ip_config or switch allows switching between any modes of the transceiver. to switch between modes, the new value of chip_config or switch should be modified when the en signal is low. the changes will be applied to the transceiver upon the rising edge of the en signal. mode swparam_mode1(1:0) or swparam_mode_2(1:0) running blocks of the transceiver sleep mode 0 0 - standby mode 0 0 quartz oscillator receiver mode 1 0 quartz o scillator, frequency synthesizer, receiver transmitter mode 1 1 quartz oscillator, frequency synthesizer, transmitter
31 d0308-214 data sheet XE1203 5.3.1 standard power up sequence for the receiver and transmitter the chip is able to switch between ever y configuration by using the 3 wires in terface (chip_config) or by using the pad switch. this section describes the switching sequenc e of the chip. the first diagram shows the sequence from sleep mode to receiver mode via stand by mode. programmed mode programmed mode programmed mode programmed mode en actual mode en actual mode sleep -> stand_by -> receiver sleep -> stand_by -> transmitter en actual mode transmitter -> receiver en actual mode receiver -> transmitter ts_os ts_re ts_os ts_tr ts_tr sleep sleep sleep stand_by stand_by stand_by stand_by transmitter transmitter sleep receiver receiver receiver transmitter receiver transmitter transmitter transmitter receiver receiver ts_re figure 15.switching between modes.
32 d0308-214 data sheet XE1203 5.4 selection of the reference frequency the reference clock used for the frequency synthesizer and in ternal digital circuit can be generated internally using internal amplifier and external quartz crystal or provided by an external oscillator. in the case of external oscillator, the register ?rtparam_osc? has to be set high, and the ex ternal clock signal at 39 mhz has to be applied to the pin ?xta?. the chip can be used with a 39 mhz quartz crys tal running on its fundamental frequency or with 3 rd overtone frequency. the third overtone operation requires a resistor in parallel to the quartz. this resistor can be selected by programming the register adparam_resxosc(3:0) . the required value depends on the crystal used. adparam_resxosc(3:0) is set to ?0000?? by default, which imposes a resistor of 3.8 mohms in parallel to the crystal. this default value is used with a 39 mhz crys tal running on its fundamental frequency. in the case of overtone operation of the quartz crystal, where the microcontroller uses the XE1203 as a clock source, user should be aware that during power up the XE1203 oscillator st arts at fundamental frequency and after programming the oscillator switch to overtone operation. therefore, a wait can be required for the oscillator to settle down before doing time sensitive operations. 5.5 clock output interface when rtparam_clkout is set high, a frequency divider by 4, 8, 16, 32, depending on adparam_clkfreq is embedded in the chip and provides the clkout clock signal for an mcu or an external circuitry. the input frequency of this divider is the 39.0 mhz reference frequency, so the possibl e output frequencies are listed in the next table. adparam_clkfreq clkout frequency 00 1.22 mhz 01 2.44 mhz 10 4.87 mhz 11 9.75 mhz when the XE1203 is in sleep mode, then this clock is stopped even if rtparam_clkout remains high. 5.6 default settings at power-up the internally generated power on reset signal sets the rtparam, fsparam, adparam and pattern registers to 00hex. only exception is clkout gener ation, although rtparam_clkout is se t to low, i.e disabled, the XE1203 generates a clkout signal in order to let the microcontroller operate. the first rising edge on en pin causes the registers to be updated and this will result clkout to be disabled. for this reason the first programming sequence should be enabli ng clkout by setting rtparam_clkout register to high for applications using clkout. initializing the XE1203 registers immediately after power-up according to the application needs is strongly recommended.
33 d0308-214 data sheet XE1203 6 application information 6.1 matching network of the receiver the schematic of the matching network at t he input of the receiver is given below rfb rfa XE1203 cr3 cr2 cr1 source lr1 the typical component values of the matching circuit are given below. name typical value for 868 mhz typical value for 915 mhz tolerance cr1 3.3 pf 1.2 pf 5 % cr2 1.5 pf 1.2 pf 5 % cr3 6.8 pf nc 5 % lr1 22 nh 27 nh 5 % 6.2 matching network of the transmitter the schematic of the matching network at t he output of the transmitter is given below. vdd
34 d0308-214 data sheet XE1203 the typical component values of the matching circuit are given below. name typical value for 868 mhz typical value for 915 mhz tolerance cr1 3.3 pf 2.2 pf 5 % cr2 3.3 pf 3.3 pf 5 % lr1 27 nh 27 nh 5 % lr2 12 nh 10 nh 5 % 6.3 vco tank the tank of the vco will be implemented with one inductor in parallel with one capacitor. the characteristics of these two components must be as follows: name typical value for 868 mhz typical value for 915 mhz tolerance cv1 0.5 pf nc 5 % lv1 12 nh 12 nh 2 % 6.4 loop filter of the frequency synthesizer the loop filter of the frequency synthesizer is shown below. cl2 XE1203 lfb rl1 cl1 the typical component values of the filter are given below. name typical value for 868 mhz typical value for 915 mhz tolerance cl1 22 nf 22 nf 5 % cl2 220 pf 220 pf 5 % rl1 2.7 k 2.2 k 5 %
35 d0308-214 data sheet XE1203 6.5 reference crystal for the frequency synthesizer for narrow band applications, where users select t he lowest frequency deviation and the narrowest baseband filter, the crystal for reference osc illator of the frequency synthesizer must have the following characteristics: name description min. value typ. value max. value fs nominal frequency - 39.0 mhz (fundamental) - cl load capacitance for fs (on-chip) - 8 pf (*) - rm motional resistance - - 40 ? cm motional capacitance - - 30 ff c0 shunt capacitance - - 7 pf (*) ? fs(0) calibration tolerance at 25 c - - 10 ppm ? fs( ? t) stability over temperature range (-40 c to 85 c) - - 10 ppm ? fs( ? t) aging tolerance in first 5 years - - 5 ppm table 5 crystal characteristics (*) the on-chip oscillator mode is user-defined by progra mming adparam_xsel: the first for cl = 8 pf and c0 = 7 pf, and the second for cl = 8 pf and c0 = 3 pf; the latter will allow higher amplitude for the internal signal with a slightly lower consumption. the electrical specifications given in section 3.2.2 are valid for a crystal havi ng the specifications given in table 5. for applications requiring less frequency stability in terms of signal bandwidth and/or temperature range, it is possible to use a crystal with larger values for ? fs(0), ? fs( ? t), and/or ? fs( ? t). in this case foffset + bwssb should be lower than bwfilter, where foffset is the o ffset (error) on the carrier frequency (the sum of ? fs(0), ? fs( ? t), and/or ? fs( ? t)), bwssb is the single side-band bandwidth of the si gnal, and bwfilter is the single side-band bandwidth of the base-band filter. the overtone crystal usage can result higher oscillator st art-up time than fundamental mode. the overtone crystal should be designed for cload = 8 to 10pf and has parameters of rm < 60 ohm, c0 < 7pf.
36 d0308-214 data sheet XE1203 6.6 typical application the simplified circuit diagram for a typical application is shown below. switch rfa rfb bpf bpf dsp unit microcontroller interface serial bus clkout pattern dataout dclk vdd 39mhz XE1203 rf transceiver /2 pll and vco
37 d0308-214 data sheet XE1203 7 packaging information XE1203 comes in a 48-lead vqfn package ? xemics 2003 all rights reserved. reproduction in whole or in part is prohibited wit hout the prior written consent of the copyright owner. t he information presented in this document does not form part of any quotation or cont ract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by t he publisher for any c onsequence of its use. publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. xemics products are not designed, intended, au thorized or warranted to be suitable for use in life-support applications, devices or system s or other critical applications. inclusion of xemics products in such applications is understood to be undertaken solely at the customer?s own risk. should a customer purchase or use xemi cs products for any such unauthorized applic ation, the customer shall indemnify and hold xemics and its officers, employees, subsidiaries, a ffiliates, and distributors harmless against all claims, costs damages and attorney fees which could arise.

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